1. Field of the Invention
The present invention relates to the manufacturing of semiconductor circuits. More specifically, the present invention relates to the structure and to the manufacturing of capacitors of metal-insulator-metal type (MIM) formed in metallization levels of interconnection of semiconductor circuits.
2. Discussion of the Related Art
MIM capacitors formed in metallization levels of interconnection of semiconductor circuits are used in a great number of applications. For example, such capacitors are used as decoupling capacitors, or as filters, for example, between two circuits or components, or in voltage-controlled oscillators or else in radio-frequency applications, or else as all or part of memory elements, for example in DRAMs . . .
FIG. 1 illustrates in cross-section view a known MIM capacitor.
The capacitor is obtained by forming, in an interlevel dielectric ILD, a first electrode E1 of the capacitor. Electrode E1 is generally formed of a line L having its bottom and its lateral walls separated from peripheral dielectric ILD by a thin layer 3 of a bonding/barrier material.
To complete the capacitor, an opening in which are successively deposited a thin insulating layer 7 and a thin layer 8 of a bonding/barrier layer, the remaining opening being filled by means of a conductor V, is formed in an interlevel dielectric IMD superposed to dielectric ILD and to line L. Insulating layer 7, barrier layer 8, and filling conductor V are removed from the upper surface of dielectric IMD. A second electrode E2 of the capacitor formed of barrier layer 8 and of conductor V and separated from the first underlying electrode E1 by insulator 7 is thus obtained.
Interlevel dielectrics ILD and IMD are generally made of silicon oxide (SiO2). Bonding layer 3 is made of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), or a multiple-layer of at least two of these conductors. Line L and conductor V are generally made of copper. Dielectrics ILD and IMD are then generally separated by a copper passivation insulating layer 10 open at the same time as dielectric IMD before the depositions of interelectrode insulator 7 and of second electrode E2.
Capacitance C of the capacitor thus obtained is proportional to electric permittivity ∈ of interelectrode insulator 7 and to surface area S opposite to electrodes E1 and E2 and inversely proportional to thickness e of insulator 7 (C=∈S/e).
To increase the value of capacitance C, it has been desired to decrease the value of thickness e. However, such a decrease comes against various limits. Especially, a limit lies in the constraint of having an interelectrode insulator 7 of homogeneous thickness. Further, a decrease in thickness e comes along with a decrease in the breakdown voltage of insulator 7. The decrease in thickness e is thus limited by the voltage difference that appears between electrodes E1 and E2. Further, a decrease in thickness e comes along with an increase in the malfunctions linked to the leakage currents.
Insulators with a significant permittivity ∈ such as, for example, hafnium oxide (HfO2, ∈=18), tantalum oxide (Ta2O5, ∈=26), or zirconium oxide (∈=22 to 25 according to the stoichiometry) or more complex oxides such as ceramics having very high permittivities, that is, greater than 100, that may reach and exceed 3,000, may also be used. However, the use of such materials with a significant permittivity ∈ raises manufacturing problems. Indeed, insulator 7 is deposited while semiconductor components, not shown, are already present in an underlying substrate. A problem lies in the fact that the deposition conditions of materials with a significant permittivity ∈ are sometimes incompatible with the presence of the components. Another problem lies in the fact that materials with a significant permittivity ∈ may be deteriorated by the subsequent component manufacturing steps, in particular by the thermal cycles. Another problem lies in the fact that it is complex to obtain a thin homogeneous layer of a material with a significant permittivity ∈ which is not polluted by contaminants which lower its real permittivity in an uncontrolled and variable fashion.
It has also been desired to increase capacitance C of the capacitor by increasing its surface area S. For this purpose, various structures have been provided to increase first electrode E1 across thickness h of interlevel dielectric ILD. Thus, a currently-used solution includes the deposition of a thin metal layer, generally of the same nature as bonding layer 3 and 8, before deposition of interelectrode insulator 7. This enables increasing electrode E1 opposite to the vertical walls of electrode E2. However, such an increase in surface area S in dielectric ILMi comes across various limits. Especially, the increasing desire to reduce the dimensions and costs of semiconductor devices results in a decrease in the thicknesses of the metallization levels. The need to increase surface area S in dielectric IMD then comes against the need to decrease its thickness h. It has then been provided to give the capacitor complex shapes aiming at increasing surface area S in dielectric IMD not only in the vertical direction, but also along the horizontal direction. However, horizontal increases come once again against the decrease in dimensions. Further, methods of conformal deposition of thin metal layers according to complex contours are relatively difficult and expensive to implement. In comparison with the improvements of the obtained electric performance, such solutions are considered as too expensive. The forming of the MIM capacitors thus becomes a major obstacle to the decrease in the dimensions of the semiconductor circuits forming them.